Apparatus and method for measuring and displaying the pulse width of a video signal

ABSTRACT

An apparatus and method is shown for measuring the width of a data pulse of a video signal containing a synchronizing pulse associated with each data pulse. Every N th  data pulse is measured and a digital representation of the measured value is displayed in standard units of length for viewing by a human observer.

This invention relates to apparatus for processing video signals and,more particularly, to such apparatus for measuring the width of a videodata pulse and providing a digital display thereof.

BACKGROUND OF THE INVENTION

Apparatus for processing video signals and measuring the actual pulsewidth of these signals typically do not provide the results of themeasurement in a form discernible to a human observer. For example, amethod of detecting weld lines is disclosed in U.S. Pat. No. 4,305,096issued Dec. 8, 1981 to Yokoshima et al. There, the video signal of theweld is compared with a reference threshold and binary coded into twosignals, one representing a dark part and one representing a light part.These binary coded signals are then input to a computer for processingby a series of mathematical algorithms to determine variouscharacteristics of the weld and to ultimately generate other signals forcontrolling the welding machine.

What would be advantageous and desirable is an apparatus and method formeasuring the pulse width of such a video signal and displaying theresults of the measurement in a form that is easily perceived by a humanobserver. Further the displayed indications should have a directcorrespondence to a standard unit of measurement, or length, such astenths of a micrometer.

SUMMARY OF THE INVENTION

According to the present invention apparatus is disclosed for providingindications at a rate which can be visually perceived by a humanobserver of the measured durations of select ones of data pulsesinterleaved in time with synchronizing pulses. The synchronizing pulsesrecur at a rate substantially higher than the rate of indication by afactor of n, n being a positive integer. The apparatus comprises:

(1) an oscillator supplying oscillations at a constant prescribed ratesubstantially higher than the data pulse durations to be measured;

(2) a counter for counting selected ones of the oscillations;

(3) a sync separator for separating the syncronizing pulses from thedata pulses;

(4) cycle selection means for selecting every N^(th) cycle of arespective syncronizing pulse followed by a respective data pulse, theduration of which is to be measured;

(5) a threshold detector for supplying indications of when the pulses,the durations of which are to be measured, exceed a threshold value;

(6) means responsive to the synchronizing pulse in each selected N^(th)cycle for resetting the counter to zero count;

(7) means responsive to the indication from the threshold detector forenabling the counter during each selected N^(th) cycle, to count theoscillations supplied to the counter from the oscillator; and

(8) display means responsive to the final count in the counter for eachselected N^(th) cycle to provide indication of the count to the humanoberver until the next selected N^(th) cycle.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a stylus point viewing and measuring systemhaving an apparatus for measuring and displaying the pulse width of avideo signal utilizing the teachings of the present invention;

FIG. 2 is a representative view of the video monitor shown in FIG. 1;

FIG. 3 is a block diagram showing the functional components of theapparatus of the present invention; and

FIGS. 4a and 4b are schematic diagrams showing the preferred embodimentof the circuits of the functional components shown in FIG. 3.

DESCRIPTION OF THE PREFERRED EMBODIMENT

With reference to FIGS. 1 and 2 there is shown a system block diagramdepicting apparatus 10 for automatically measuring the length of theshoe of a video disc stylus. This apparatus is the subject of acopending application of John A. van Raalte filed concurrently with thepresent application, and entitled "Apparatus and Method forAutomatically Measuring the Shoe-Length of a Video Disc Stylus" andhaving the No. 574 462.

The apparatus 10 includes a microscope 12 having a 1000X eyepiece 13arranged to focus on the point 14 of a stylus 16 which is held inoperating position within a stylus holder 18. A standard industrial TVcamera 26, such as a one-inch RCA Nuvicon Camera (type N-1005), ispositioned at a fixed distance from the eyepiece 13 so that the camera26 may focus on the stylus point 14 through the optics of the microscope12. The output of the camera 26 is displayed on a TV monitor 30.Magnification of the image received by the camera 26 may be increased to3000X or even 5000X by simply inserting another lens 28 of theappropriate focal length at a point approximately two inches from theNuvicon tube. In this way the size of the image displayed on the monitor30, may be adjusted for comfortable viewing by an operator, independentof the actual size of the stylus point 14 that is being measured. Asbest seen in FIG. 2, an image 32 of the stylus point 14 is shown havinga shoe 34 and two adjacent keel shoulders 36.

The video signal from the camera 26 which is displayed on the TV monitor30, is first directed to a video slicer 40 which displays a verticalsampling line 42 on the monitor. By manipulating certain controlsassociated with the video slicer 40, the operator can move the samplingline 42 over the image 32 of the stylus point 14 until the line 42 isdirectly over the portion of the image whose length is to be measured.Since the images of the shoe 34 and keels 36 are the only bright objectsin the field of view of the camera 26, when the sampling line 42 ispositioned as shown in FIG. 2, the line 42 traverses dark regions aboveand below the bright image of the shoe 34. The video slicer 40 detectsthese differences in brightness and generates a video signal 50corresponding thereto. An image 38, being a graphical representation ofthe signal, is displayed on the monitor 30 in a position horizontally inline with the image 32 as shown in FIG. 2. The amplitude of the image 38represents the brightness along the sampling line 42 and the width W ofthe pulse as shown in FIG. 2, represents the length of the brightobject, in this case the shoe 34. Similarly, the signal 50 includes adata pulse 52 having an amplitude representing the brightness of theobject in the field of view of the camera 26 and a pulse widthrepresenting the length of the bright object. The signal 50 furtherincludes synchronizing pulses 54 for identifying each video frame. Thissignal 50 is directed to a sampling and display circuit 58 which is thesubject of the present invention.

A block diagram of the sampling and display circuit 58 is shown in FIG.3. Each block of the block diagram is also represented in one of FIGS.4a and 4b as dashed lines and is identified with a like lead number. Forexample, the amplifier 60 shown in FIG. 3 represents the circuitryenclosed in the dashed lines 60 shown in FIG. 4a.

With reference to FIGS. 3, 4a, and 4b, the signal 50, which is astandard NTSC video signal, is input at 62 to the DC coupled amplifier60 which comprises the three transistors Q1, Q2, and Q3, and relatedcircuitry. This related circuitry is well known in the art and will notbe described here. The signal 50 has an amplitude of approximately 0.5 Vpeak to peak as applied to the base 64 of the transistor Q1. Thetransistors Q1, Q2 and Q3 amplify the signal 50 to 6 volts peak to peakand output an amplified signal 68 at the emitter 66 of the transistorQ3. The transistor Q3 functions as an emitter follower in a manner wellknown in the art for providing increased power output. The amplifiedsignal 68 is then directed to a threshold detector 70.

The threshold detector 70 comprises a comparator 72, a bias leveladjustment 74 and related circuitry which is well known in the art andwill not be described here. A preset bias voltage of approximately onevolt, which may be adjusted by manipulating the bias level adjustment74, is applied to the non-inverting positive input terminal 76 of thecomparator 72. The amplified signal 68 is applied to the input terminal78 of the comparator 72 and if it is equal to or exceeds the preset biasvoltage, the output terminal 80 is caused to go high. This results in asquare wave output signal 82 appearing on the output terminal 80. Thesignal 82 will have the same pulse width as the data pulse 52 of thevideo signal 50 at the one volt bias level. This type of comparator iswell known in the art and will not be described further here. The zenerdiode 88 clamps the plus D.C. high voltage level appearing on the output80 to an approximate maximum of five volts. This voltage level shift isperformed to provide a signal compatible with the transistor totransistor logic (TTL) plus 5 VDC voltage level required by commerciallyavailable counting conversion logic to be described below. This signalthen becomes the input to the gate 90.

An oscillator 92 comprising a NAND gate 94, a potentiometer 96, and acapacitor 95 form what is known in the art as a relaxation oscillatorfor generating oscillations 97 at the rate of 39.5 KHZ on the output100. This signal, along with the signal 82 appearing on the outputterminal 80 of the comparator 72 is impressed on the input of the gate90. The gate 90 comprises a pair of NAND gates 110 and 112. As thesignal 82 from the comparator 72 goes high the NAND gate 110 is enabledwhich allows the positive side of the oscillations 97 from theoscillator 92 to pass through to the output 120 of the NAND gate 110 inbursts. These bursts from the output signal 98 which in turn, is inputto the NAND gate 112 for inversion and passed on to the output 122.Disposition of the signal 98 appearing on the output 122 will bedescribed later.

With reference to the amplifier 60, an output 130 is provided having anamplification of the video signal 50 which appears on the collector 132of the transistor Q1. This amplified signal 50 is input to a syncseparator 136 for removing the data pulses 52, leaving only thesynchronizing pulses 54. The sync separator 136 comprises an inverter140, a buffer 142, and a negative feed back diode 144 arranged inparallel with the inverter 140, as shown in FIG. 4A. The diode 144causes the inverter 140 to operate at the mid-range of its operatingvoltage level. Thus, when the sync pulses 54, which have a voltage levelcorresponding to the quiescent point of the inverter 140, appear on theinput 146 of the inverter 140, the output 148 is reduced by about 5volts which is sufficient to drive the buffer 142 to output full voltageat the output 150. Conversely, as data pulses 52, which have a voltagelevel below the quiesent point of the inverter 140, appear on the input146, the output 148 undergoes a relatively small change of about twovolts which is insufficient to drive the buffer 142. Therefore, thesignal 152 appearing on the output 150 contains only the sync pulses 54of the video signal 50.

The signal 152 is applied to an input 154 of an N^(th) cycle selector160 which generates, on the output 162, a signal 180 for every N^(th)synchronizing pulse 54 that is detected on the input 154. The N^(th)cycle selector 160 comprises an IC binary (shift register) counter 164of a type that is commercially available, such as RCA part numberCD4024, and a standard flip-flop 166. The counter 164, having a seriesof seven output terminals 171, 172, 173, 174, 175, 176, and 177,receives the signal 152 on the input 154 and counts the number ofsynchronizing pulses 54. For every four synchronizing pulses counted theoutput terminal 171 will alternately go high for two pulses and then lowfor two pulses. For every eight synchronizing pulses the terminal 172will alternately go high for four pulses and then low for four pulses.Similarly, for the appropriate number of synchronizing pulses the outputterminals 173-177 will go high for 8, 16, 32, 64, and 128 pulsesrespectively and then low for the same duration. One of these outputterminals 171-177 is connected to the input 168 of the flip-flop 166.When a high is received on the input 168, the flip-flop 166 is set andwill output a high on the output terminal 162 and will maintain thishigh independent of subsequent changes in state of the signal on theinput terminal 168 until the flip-flop 166 is reset by receiving asignal on the input terminal 170 at which time the output terminal 162will go low.

The signal 152, in addition to being applied to the counter, or shiftregister 164, is also applied to the flip-flop 166 at the input terminal170. The flip-flop 166 is responsive to the leading edge 169 of thesynchronizing pulse 54 and will reset upon detecting this edge. Withthis arrangement, the N^(th) cycle selector will output a pulse at theterminal 162 for every 2nd, 4th, 8th, 16th, 32nd, 64th, or 128thsynchronizing pulse detected on the input 154, depending on which outputterminal 171-177 is utilized. In the present invention the outputterminal 175 was selected for use for reasons given below. In this case,when 16 synchronizing pulses are counted by the counter, or shiftregister, 164 the terminal 175 will go high causing the input 168 toalso go high thereby setting the flip-flop 166 which outputs a signal180 on the output terminal 162. The very next synchronizing pulse 54received on the input 170 resets the flip-flop 166 causing the output162 to go low so that the signal 180 is generated as a square wave formhaving a pulse width K which is equal to the distance between adjacentsynchronizing pulses 54 of the signal 50. The terminal 175 will stayhigh until until 14 more synchronizing pulses are received at which timeit will go low for 16 additional synchronizing pulses, all of which haveno effect on the state of the flip-flop 166. The next synchronizingpulse, that is the 33rd pulse, will again set the flip-flop 166 therebybeginning a new N^(th) cycle. In this way the signal 180 contains asingle pulse for every 32 synchronizing pulse 54 that are contained inthe video input signal 50, each single pulse having a width K.

The signal 180 output by the N^(th) cycle selector and the signal 98output by the gate 90 are applied to the input terminals 190, 192respectively of the NAND gate 196. In the case of the present invention,the gate 196 is enabled for one cycle upon detection of every 32nd cycleof the video input signal 50 and a single burst of the signal 98 ispassed to the output 198 of the gate 196.

The signal 98 from the output 198 of the gate 196 is passed to thecounter 200, see FIG. 4b, for counting the oscillations contained withina given burst. The counter 200 includes a pair of series connected fourbit burst counters 210 and 212 each of which has its output connected toa latching register 214 and 216 respectively, and a pair of monostablemultivibrators 220 and 222, as shown in FIG. 4b. The monostablemultivibrators 220 and 222 are commercially available integratedcircuits such as Texas Instrument part number 74LS123N. With the gate196 enabled, the signal 98 is applied to the input 224 of the burstcounter 210 which counts the oscillations generated by the oscillator92. Overflow is passed in series to the burst counter 212. The counter210 outputs a four bit BCD code representing the units position to thelatch register 214 and the counter 212 outputs a four bit BCD coderepresenting the tens position to the latch register 216.

The signal 181 appearing on the output terminal 163 of the flip-flop 166is passed to the input terminal 244 of the multivibrator 220. Thiscauses the multivibrator 220 to output a signal 240, having a relativelynarrow pulse, to the input terminals 246 and 248 of the latch registers214 and 216 respectively. The transfer of the four bit BCD codes fromthe counters 210 and 212 to the latch registers 214 and 216 is effectedwhen the latch registers detect the signal 240. The BCD codes sotransferred will appear on the output terminals 250 and 252 and remainthere until the N^(th) cycle selector 160 generates the next signal 180and signal 181 representing the N^(th) plus first cycle. The BCD codesappearing on the output terminals 250 and 252 are passed to a digitaldisplay 261 and are connected to a pair of digital readout units 256 and258 for displaying the numeric values of the BCD codes when the unitsare enabled. These digital readout units may be any suitablecommercially available display devices such as that supplied by HewlettPackard as part number 5082-7340.

The multivibrator 220 also generates a signal 260 on the output terminal262 which is input to a third multivibrator 264. This signal 260indicates that the oscillations of the signal 98 has been totaled by theburst counters 210 and 212 and has been successfully transferred to thelatch registers 214 and 216. This causes the multivibrator 264 togenerate two output signals 270 and 272. The first of these signals,signed 270, which appears on the output terminal 271, is passed to thedigital readout units 256 and 258 which are enabled upon detection ofthe signal. The signal 270 is also impressed onto the input terminal 280of the multivibrator 222. Upon detection of this signal themultivibrator 222 will reset the burst counters 210 and 212 which arenow ready to receive a new burst of oscillations from the gate 196representing the next N^(th) cycle. The second of these signals, signal272, which appears on the output terminal 273, is passed to an outputdriver 280 and is connected directly to a strobe driver 283 whichindicates that data is present on the output drivers 281 and may beinterrogated by some other peripheral device 290 such as a computer orthe like. The data appearing at the output drivers 281 is parallelcoupled at 282 to the output terminals 250 and 252 of the latchregisters 214 and 216 in a manner that is well known in the art.

The number of standard oscillations of the signal 98 that will appear onthe output 120 of the gate 90 is determined by the length of time thatthe NAND gate 110 is enabled by the signal 82 from the thresholddetector 70. Each pulse of the signal 82 has a pulse width that exactlycorresponds to the width of the data pulse 52 of the video input signal50 at a reference amplitude of one volt. Therefore, the signal appearingon the output terminal 120 of the NAND gate 110 will include a burst ofoscillations, the number of which also will exactly correspond to thewidth of the data pulse 52 at one volt.

The digital output of the two display modules 256 and 258 can be made todirectly correspond to tenths of a micrometer by tuning the basefrequency of the oscillator 92 by a method that is well known in theart. In this way a direct read out in tenths of a micrometer of thelength of the image 32 along the sampling line 42 is displayed forviewing by the operator. Furthermore, the sampling rate of one displayrefresh every 32 cycles, permits relative stability in the display withlittle flicker thereby permitting visual perception by a human observer.

I claim:
 1. Apparatus for providing indications at a rate which can bevisually perceived by a human observer of the measured durations ofselected ones of data pulses interleaved in time with synchronizingpulses, which synchronizing pulses recur at a rate substantially higherthan said rate of indication by a factor of n, n being a positiveinteger, said apparatus comprising:a. an oscillator supplyingoscillations at a constant prescribed rate substantially higher than thedata pulse durations to be measured; b. a counter for counting selectedones of said oscillations; c. a sync separator for separating saidsynchronizing pulses from said data pulses; d. N^(th) means forselecting every N^(th) cycle of a respective synchronizing pulsefollowed by a respective data pulse, the duration of which is to bemeasured; e. a threshold detector for supplying indications of when thepulses, the durations of which are to be measured, exceed a thresholdvalue; f. means responsive to the synchronizing pulse in each selectedN^(th) cycle for resetting said counter to zero count; g. meansresponsive to said indication from said threshold detector for enablingsaid counter during each selected N^(th) cycle, to count saidoscillations supplied to said counter from said oscillator; and h.display means responsive to the final count in said counter for eachselected N^(th) cycle to provide indications of said count to said humanobserver until the next selected N^(th) cycle.
 2. The apparatus as setforth in claim 1 wherein said prescribed rate of oscillations suppliedby said oscillator, said counter for counting said oscillations, andsaid display means responsive to the final count of said counter arearranged so that said indications are in standard units of length. 3.The apparatus set forth in claim 2 wherein said standard units of lengthare tenths of a micrometer.
 4. The apparatus set forth in claim 3wherein said N^(th) cycle selector means comprises a binary shiftregister and a flip-flop wherein said binary shift register responsiveto every said N^(th) cycle of a respective synchronizing pulse outputs asignal on a first input to said flip-flop for enabling said flip-flopand wherein said flip-flop is disabled when a next synchronizing pulseis detected on a second input to said flip-flop.
 5. A method ofmeasuring the width of a data pulse of a video signal having asynchronizing pulse associated with each data pulse comprising:(a)amplifying said video signal; (b) detecting if said data pulse to bemeasured exceeds a threshold value and generating a square wave signalcorresponding thereto; (c) supplying a signal having oscillations at aconstant prescribed rate substantially higher than the data pulsedurations to be measured; (d) gating said signal having oscillationswith said square wave signal and generating a signal having bursts ofoscillations, the number of which corresponds to the width of the datapulse to be measured; (e) selecting every N^(th) burst of oscillationsfrom said signal having bursts of oscillations; (d) counting saidoscillations of the selected said N^(th) burst of oscillations anddisplaying the final count of said counting for viewing by a humanobserver.
 6. The method set forth in claim 5 wherein step (e) includes:(1) counting said synchronizing pulses and upon counting every N^(th)one enabling said counting of said oscillations and (2) disabling saidcounting of said oscillations upon detecting every N^(th) +1 of saidsynchronizing pulses.
 7. The method set forth in claim 6 wherein step(c) includes supplying a signal having oscillations at a rate so thatsaid displaying of said final count in step (d) is indicated in standardunits of length.